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[招聘] Cadence 招聘数字前端产品工程师

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发表于 2017-11-24 18:13:25 | 显示全部楼层 |阅读模式

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Title: Lead Product Engineering (数字前端)

Job location: Shanghai

更多职位信息敬请关注Cadence公众微信平台:Cadence微招聘


If you have interest, PLS send your update CV to job_china@cadence.com


LeadProduct Engineering


PositionDescription:     

Thisis a unique opportunity to join the rapidly growing Product Engineering team inthe IP Group at Cadence Design Systems. We are looking for a Lead ProductEngineer who will be the main technical interface on Key Customer engagements deployingour advanced high speed PHY IP.  This isa hands on technical position.  The candidatemust have experience successfully integrating and/or designing high speed PHYIP in an SOC and product level environment.

MainJob Tasks and Responsibilities:

  • Main     technical interface between R&D team and tier one customer design     teams using advanced high speed PHY IP.
  • Primary technical contact for customer     SOC and system integration questions.
  • Support customer SOC teams from RTL and     PHY integration to final GDS, and production ramp.
  • Primary technical link between R&D     team and Field Application Engineers
  • Generate     technical specification, data sheets, and application notes.
  • Update R&D     teams with the latest customer feedback and competitive analysis.
  • Drive and     support Customer silicon evaluations and demos.
  • Support the entire IP product delivery     cycle starting at initial presales stages.
  • Work with     R&D, Marketing, and sales teams to create technical proposals.

                                               

PositionRequirements:              

  • M.S.     Electrical/Computer Engineering (or similar degree)
  • 7+ years     experience developing or using high speed PHYs (8Gbps+)
  • Experience     working with USB, SATA, PCIe, or Ethernet protocols.
  • Experience     using advanced mixed signal verification, and system simulation tools.
  • Experience     in SOC design implementation, from RTL to final GDS, and production ramp.
  • Verilog     design and static timing close experience.
  • Experience with industry standard DFT     flows and methodologies.
  • Strong     Exposure to all major IC implementation, design, verification, and debug     tools.
  • Strong debug and problem solving skills
  • Hands on experience with high speed     scopes and signal analysis equipment      is a plus
  • Familiarity     with advanced technology nodes (16nm and below) is a plus
  • Must have     strong group presentation skills.

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