snug2007文章一篇－JupiterXT Timing Budgeting

giadashan · 发表于 2010-6-28 16:01:32

学习学习

edatraining · 发表于 2010-6-28 16:21:42

刚好要招个懂这个的人
有没有有兴趣的.

Requisition Description:
The Candidate will be responsible for physical hierarchy flow's development and comprehensive advanced feature testing of Synopsys IC Compiler. Good knowledge of high-level hierarchy design methodologies, Include hierarchy mcmm flow,Hierarchy UPF low power flow.And the candidate should be able to develop tools/scripts to constantly improve testing process efficiency and product quality.

BS with 5+ years of relevant experience , MS with 3+ years of relevant experience, or related Ph.D with 1+ years of experience.
Strong communication. Proficient Physical Hierarchy design methodology or a strong understanding of ASIC design flows . Knowledge of cimpetitive EDA tool products and product knowledge in the areas of place and route,Design Reuse and/or Physical Design is highly desired.

If you are interested in it, Please email you resumes to aspc1234@yahoo.com.cn

Synopsys是世界第一的EDA软件公司主要面的客户是一流的ASIC design 公司（Intel,ST,LSI,Toshiba....) 特别是超大规模的数字前端/后端设计.
新一代的后端EDA 软件 IC complier 已经可以支持32nm 下的后端设计。同时最大的Tapeout 达到4000万个 Cell instance.（~1.6亿个gate), Physical Hierarchy design 占据着越来越重要的角色

sikanglu · 发表于 2010-7-16 20:55:27

谢谢分享！

wwei10619 · 发表于 2011-3-1 23:51:18

好东西，谢谢。

crazyfind · 发表于 2011-3-16 03:48:11

take a look

ggouhwpb · 发表于 2011-4-6 09:58:01

youyongmanengkanma

wangyongan · 发表于 2017-4-16 16:50:21

好资料

snug2007文章一篇－JupiterXT Timing Budgeting

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