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简历请发derek.yin@ovt.com
Responsibilities:
- Responsible for the setup and development ofthe front-end design environment and flow. - Responsible for the front-end design check,logic synthesis, power analysis and STA.
- Responsible for the full chip DFT strategy andDFT plan define.
- Responsible for the DFT implementation,verification and chip validation of the IPs and SOC design.
- Responsible for the ATE chip bring up andfailure analysis.
Requirements:
- BSEE required, MSEE preferred, with basic ASICdesign knowledge.
- Familiar with the ASIC design flow andexcellent understanding on DFT concepts.
- Handy experience on mainstream DFT EDA tool(Synoposys, Mentor) to implement and verify DFT design is a plus.
- Knowledge on design synthesis, front-enddesign rule checks and STA.
- Familiar with Programming in Perl, tcl andC/C++
- Strong and continuous learning capability,self-motivated and good communication skill. |