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发表于 2018-2-23 09:10:02
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session list
CICC Technical Program
Session 1 - Plenary
Session 2 - Wireline Techniques forAdvanced Modulation Schemes
2-1 A Supposedly Clever Thing I’ll Never Do Again, Aaron Buchwald, Inphi
2-2 Channel Adaptive ADC and TDC for 28 Gb/s 4pJ/bit PAM-4 Digital receiver,
2-3 A 4-40 Gb/s PAM4 Transmitter with Output Linearity Optimization in 65 nm CMOS,
2-4 A 10-to-650MHz 1.35W Class-AB Power Amplifier with Instantaneous Supply-
Session 3 - Clocking Techniques
3-1 A 0.951 psrms Period Jitter, 3.2% Modulation Range, DSM-Free, Spread-Spectrum
3-2 A 0.031mm2, 910fs, 0.5-4GHz Injection Type SOC PLL with 90dB Built-in Supply
Noise Rejection in 10nm FinFET CMOS, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien
Chang, Kenny Hsieh, Mark Chen, TSMC
3-3 A -236.3dB FoM Sub-Sampling Low-Jitter Supply-Robust Ring-Oscillator PLL for
Clocking Applications with Feed-Forward Noise-Cancellation, Shravan S. Nagam,
Peter R. Kinget, Columbia University
3-4 Second and Third-Order Successive Requantizers for Spurious Tone Reduction in
Low-Noise Fractional-N PLLs, E. Familier, I. Galton, University of California, San Diego
3-5 A 45-75MHz 197-452u W Oscillator with 164.6dB FoM and 2.3psrms Period Jitter in
65nm CMOS, J. Zhu, M. Mahalley*, G. Shu, W.-S. Choi, R.K. Nandwana, A. Elkholy, B.
Sahoo, P.K. Hanumolu, University of Illinois at Urbana Champaign, *Analog Devices
Session 4 - Modeling and Measurement of Mixed-Signal Circuits
4-1 Modelling Multistability and Hysteresis in ESD Clamps, Memristors and other
Devices, Tianshi Wang, Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley
4-2 A Yield Optimization Methodology for Mixed-Signal Circuits, A. Papadopoulou, B.
Nikolic, University of California at Berkeley
4-3 Measurement of High-Speed ADCs, L. Kull*, D. Luu*,**, IBM Research - Zurich, ETH
Zurich
Session 5 - Memory for Emerging Applications
5-1 A 0.13μm 64Mb HfOx ReRAM Using Configurable Ramped Voltage Write and Low
Read-Disturb Sensing Techniques for Reliability Improvement
5-2 Programmable Supply Boosting Techniques for Near Threshold and Wide
Operating Voltage SRAM
5-3 12x Bit-Error Acceptable, 300x Extended Data-Retention Time, Value-Aware SSD
with Vertical 3D-TLC NAND Flash Memories for Image Recognition
5-4 A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using
Multiple Read/Write Assists and VMIN Tracking Canary Sensors
5-5 An Offset-Cancelling Four-Phase Voltage Sense Amplifier for Resistive Memories
in 14nm CMOS
Session 6 - RF and Millimeter-Wave Power Amplifiers and Transmitters
6-1 Millimeter-Wave Power Amplifiers & Transmitters
6-2 A 3-7GHz 4-Element Digital Modulated Polar Phased-Array Transmitter with 0.35°
Phase Resolution and 38.2% Peak System Efficiency
6-3 Linearization of Multiphase SCPAs
Session 7 - Data Converter Techniques
7-1 A 6-bit 0.81mW 700-MS/s SAR ADC with Sparkle-Code Correction, Resolution
Enhancement, and Background Window Width Calibration
7-2 A Pipelined SAR ADC Reusing the Comparator as Residue Amplifier
7-3 A 74.33 dB SNDR 20 MSPS 2.74 mW Pipelined ADC using a Dynamic Deadzone
Ring Amplifier
7-4 A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm Using Novel Residue Boosting
7-5 A Background Calibrated 28GS/s 8b Interleaved SAR ADC in 28nm CMOS
7-6 A 10-b 2b/cycle 300MS/s SAR ADC with a Single Differential DAC in 40nm CMOS
7-7 A 73dB SNDR 20MS/s 1.28mW SAR-TDC Using Hybrid Two-Step Quantization
Session 8 - Biomedical Circuits and Systems
8-1 Design of Miniaturized Wireless Power Receiver for mm-sized implants
8-2 A Power-Efficient Multi-Channel PPG ASIC with 112dB Receiver DR for Pulse
Oximetry and NIRS
8-3 A Dynamically Reconfigurable ECG Analog Front-End with a 2.5× Data-Dependent
Power Reduction
8-4 CMOS Sensor for Dual Fluorescence Intensity and Lifetime Sensing Using
Multicycle Charge Modulation
8-5 A 255nW Ultra-High Input Impedance Analog Front-End for Non-contact ECG
Monitoring
8-6 A Front-End ASIC with High-Voltage Transmit Switching and Receive Digitization
for Forward-Looking Intravascular Ultrasound
8-7 Interference-immune Diagnostic Quality ECG Recording for Patient Monitoring
Applications
8-8 A CMOS 22k-Pixel Single-Cell Resolution Multi-Modality Real-Time Cellular
Sensing Array
Session 9 - Panel - Hardware and Software Security: Gaps and Synergies
Session 10 - Forum - MM-wave and Wide Band Circuits for 5G Communications and Automotive
Session 11 - Wireline Building Blocks
11-1 A 10 GHz 56 fsrms-Integrated-Jitter and -247 dB FOM Ring-VCO Based Injection-
Locked Clock Multiplier with a Continuous Frequency-Tracking Loop in 65 nm
CMOS
11-2 Jitter Injection for On-Chip Jitter Measurement in PI-Based CDRs, J. Liang, A.
Sheikholeslami
11-3 A 27.1 mW, 7.5-to-11.1 Gb/s Single-Loop Referenceless CDR With Direct Up/dn
Control
11-4 A 40-Gbps 0.5-pJ/bit VCSEL Driver in 28nm CMOS with Complex Zero Equalizer, A.
Sharif-Bakhtiar
11-5 Low-Power CMOS Receivers For Short Reach Optical communication
Session 12 - Analog Techniques I
12-1 A 0.5V Supply, 49nW Band-Gap Reference and Crystal Oscillator in 40nm CMOS
12-2 A Start-up Boosting Circuit with 133x Speed Gain for 2-Transistor Voltage
Reference
12-3 A Precisely-Timed Energy Injection Technique Achieving 58/10/2µs Start-Up in
1.84/10/50MHz Crystal Oscillators
12-4 A 0.7V Time-based Inductor for Fully Integrated Low Bandwidth Filter Applications
12-5 A 0.65mW 20MHz 5th-Order Low-Pass Filter with +28.8dBm IIP3 Using Source
Follower Coupling
Session 13 - Security Circuits and Systems
13-1 Energy Efficient and Ultra Low Voltage Security Circuits for Nanoscale CMOS
Technologies,
13-2 A DRAM based Physical Unclonable Function Capable of Generating >10^32
Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication
13-3 Trustworthy System-on-Chip Design for Internet of Things, Sandip Ray, NXP
Semiconductors
13-4 An Area-Efficient Microcontroller with an Instruction-Cache Transformable to an
Ambient Temperature Sensor and a Physically Unclonable Function, Teng Yang,
Jiangyi Li, Minhao Yang, Peter R. Kinget, Mingoo Seok, Columbia University
This paper presents an very area-efficient SoC design with ambient temperature sensing
and PUF operations based on a unique transformation of microcontroller's I$ to
temperature sensor and PUF. It has comparable performances to the state-of-the-art but
consumes 9.8X smaller sensor frontend area.
Session 14 - Forum - Self-Sustaining IoTs - Fact or Fiction
Session 15 - Energy Efficient Wireless for 5G and IoT
15-1 Energy Efficiency Maxima for Wireless Communications: 5G, IoT, and Massive
MIMO
15-2 An Ultra-Low-Power Wake-Up Receiver with Voltage-Multiplying Self-Mixer and
Interferer-Enhanced Sensitivity, Vivek Mangal, Peter R. Kinget, Columbia University
15-3 A 6.1mW 5Mb/s 2.4GHz Transceiver with F-OOK Modulation for High Bandwidth
and Energy Efficiencies
Session 16 - Switching Regulators
16-1 A Digital Pulse Width Modulation Closed Loop Control LDMOS Gate Driver for LED
Drivers Implemented in a 0.18µm HV CMOS Technology
16-2 A 10MHz 2mA-800mA 0.5V-1.5V 90% Peak Efficiency Time-Based Buck Converter
with Seamless Transition between PWM/PFM Modes, S. J. Kim, W. Choi, R. Pilawa,
P. K. Hanumolu, University of Illinois at Urbana-Champaign
Session 17 - Non-Traditional Computing Hardware
Session 18 - Panel - Your Favorite Analog/Mixed-signal/RF Circuits
Session 19 - High-Performance and Low-Power Frequency Generation
Session 20 – High-Performance Low-Power Wireless Receivers
20-1 N-path filters and Mixer-First Receivers: A Review
20-2 A Digital Sine-Weighted Switched-Gm mixer for Single-Clock Power-Scalable Parallel Receivers
20-3 A Scalable Architecture for Fully Integrated Multi-TV Tuners
20-4 A LTE RX Front-end with Digitally Programmable Multi-Band Blocker Cancellation in 28nm CMOS
20-5 A 980μW 5.2dB-NF Current-Reused Fully Integrated Direct-Conversion Bluetooth-Low-Energy Receiver in 40nm CMOS
Session 21 – Analog Techniques II
Wednesday, May 3, 9:00 – 12:00, Lady Bird 2 Room
21-1 A ±5V, ±10V, ±15V, 4-Channel Class-G Biphasic Constant-Current Stimulator
21-2 From Algorithms to Devices: Enabling Machine Learning through Ultra-Low-Power VLSI Mixed-Signal Array Processing
21-3 Design of Tunable Digital Delay Cells
21-4 RC-Triggered ESD Clamp with Low Turn-on Voltage
21-5 A CMOS Pixel Design with Binary Space-time Exposure Encoding for Computational Imaging
22-1 An 84 dB Dynamic Range 62.5-625 kHz Bandwidth Clock-Scalable Noise-Shaping SAR ADC with Open-Loop Integrator using Dynamic Amplifier
Session 22 – Oversampling Data Converter
Wednesday, May 3, 9:00 – 12:00, Lady Bird 3 Room
22-2 A 2.4mW, 111 dB SNR Continuous-time ΣΔ ADC With A Three-level DEM Technique
22-3 A 50 MHz BW 73.5 dB SNDR Two-stage Continuous-time ∆Σ Modulator with VCO Quantizer Nonlinearity Cancellation
22-4 Adaptive Digital Noise-Cancellation Filtering using Cross-Correlators for Continuous-Time MASH ADC in 28nm CMOS
22-5 An 11.0 bit ENOB, 9.8 fJ/conv.-step Noise-Shaping SAR ADC Calibrated by Least Squares Estimation
22-6 A Two-Capacitor SAR-Assisted Multi-Step Incremental ADC with a Single Amplifier Achieving 96.6 dB SNDR over 1.2 kHz BW
22-7 A 1.2 V, 0.84 pJ/Conv.-Step Ultra-low Power Capacitance to Digital Converter for Microphone based Auscultation
Session 23 – Panel – Bio-inspired Learning and Inference Systems: What Works Well and What Didn’t
Session 24 – Millimeter-Wave Communication Circuits
24-1 Millimeter-wave Full-Duplex Wireless: Applications, Antenna Interfaces and Systems
24-2 A Bidirectional Lens-Free Digital-Bits-In/-Out 0.57mm2 Terahertz Nano-Radio in CMOS with 49.3mW Peak Power Consumption Supporting 50cm Internet-of-Things Communication
24-3 An Efficient 291 GHz Signal Source with 1.75 mW Peak Output Power in 65 nm CMOS
24-4 An up to 36Gbps Analog Baseband Equalizer and Demodulator for mm-Wave Wireless Communication in 28nm CMOS
Session 25 – Linear Regulator Techniques
25-1 Digitally-Assisted Leakage Current Supply Circuit for Reducing the Analog LDO Minimum Dropout Voltage
25-2 An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate
25-3 Digitally Controlled Voltage Regulator Using Oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS
Session 26 – Forum – Emerging Techniques for Data Converters
Session 27 – Technology Directions
27-1 Flexible Selfbiased 66.7nJ/c.s. 6bit 26S/s Successive-Approximation C-2C ADC with Offset Cancellation using Unipolar Metal-Oxide TFTs
27-2 Smart-Wire: A 0.5V 44uW 0°C to 100°C Powerline Energy Harvesting Sensor Node
27-3 A Monolithically Integrated, Optically Clocked 10GS/s Sampler with a Bandwidth of > 30GHz and a Jitter of < 30fs in Photonic SiGe BiCMOS Technology
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