Cadence 招聘前端设计资深工程师

kengteng

Title: Principal/Lead/SeniorDesign Engineer (数字前端设计)

Joblocation: Shanghai/Beijing

更多职位信息敬请关注Cadence公众微信平台：Cadence微招聘

If you have interest, PLS send your update CV to job_china@cadence.com

Position Description:

Deliver/implementHBM IP. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

- Beresponsible for building and leading a high-performance IC design team, owningthe IC micro-architecture, package and test platform development, refining theEDA design flow

-Proficiency in logic design, simulation, synthesis, STA and testing

-Proficiency in Verilog and its simulation environment

- Goodknowledge of IC design

* At leastfive years experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.

  

PositionRequirements:

1. Essential Qualifications: Must have BS degreewith 6+ years of applicable experience, MS degree with 4+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

2. Essential that the individual demonstratesstrong communication, verbal and written. 3. Requires good communication skillsin English.