ISE报的错误不知道如何解决，有谁能救救我？？？

mslzt

程序在Altera的芯片上正常工作，现在用在XC6SLX16芯片上，在ISE中报的错误如下，不知道如何解决，有谁知道怎样解决这个问题吗？

在UCF文件中添加< NET "iRESET" CLOCK_DEDICATED_ROUTE = FALSE; >之后不再报错，但FPGA无法正常工作。

[Place 1108] A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
The clock IOB component <iRESET> is placed at site <H2>.
The corresponding BUFG component <iRESET_IBUF_BUFG> is placed at site <BUFGMUX_X3Y8>.
There is only a select set of IOBs that can use the fast path to the Clocker buffer,
and they are not being used. You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design,
you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However,
the use of this override is highly discouraged as it may lead to very poor timing results.
It is recommended that this error condition be corrected in the design.
A list of all the COMP.PINs used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to override this clock rule.
< NET "iRESET" CLOCK_DEDICATED_ROUTE = FALSE; >