Marvell 美满电子招聘，后端，验证，前端，FAE等大量职位等待你的加入

sivilar

经过一段时间的调整后，Marvell现有的各部门都整装待发，重新进入了组建大团体的时代。现有大量职位空缺等待各位能人的加入。我司待遇算得上行业靠前，每年又有股票等奖励，性价比高。欢迎大家讲简历投至 sivilar@126.com，来信请标明来自EETOP和所投岗位名称。

现主力大规模招募：
数字后端: Physical Design Engineer/Staff Physical design Engineer/Senior Physical design Engineer 工作地点：上海
数字验证: Senior Manager, Design Verification/Senior Engineer, Design Verification/Staff Engineer, Design Verification/Engineer, Design Verification 工作地点：上海

其他岗位空缺可见附件，想咨询详细JD的可发站短
[url=]Marvell recruitment.pdf[/url]


Engineer需要1-2年工作经验，senior 3-5年， staff 5-7年以此类推。如果是原来做的其他方向现在想转方向，只要是design相关，熟悉基本概念基本原理都可以来尝试一下。

Physical Design general的JD
Responsibility:

Implementing from Synthesis to GDSII that includes synthesis/Scan Insertion/P&R/ timing signoff/physical signoff and all variety check for Higher QoR
Power fixing based on power analysis result
Develop methodologies to make daily work more efficient
Cooperate with designers on RTL issues which relative to backend timing closure and congestion solve.
Debugging the flow to make it advance.

Experience:
Have DRC/LVS/ERC/Antenna debugging skills
Knows Cadence/Synopsys Implement flow such as DCT/ICC or Genus/Innovus flow.
Good programming skill.
Understanding the DFT concept w/ scan chain insertion.
Knows low power methodologies for BE implement.
Capable of writing Tcl or Perl.
Familiar with synthesis, static timing analysis, Understanding timing signoff w/ Primetime or Tempus.
Familiar with RTL Design in Verilog is a plus.
Self-motivated team worker, good verbal and written communication skills in English.


Design Verification general的JD
Responsibility:
      Work with architecture and designers to get a full deep insight on the design under verification.
      Subsystem/Chip level state of the art verification, test bench setup/maintain and methodology deployment
      Test case creation to ensure coding coverage meet target      Provide clear status of chip verification progress and issues to management.

Experience:
        Knowledge of Verilog/SV/UVM
        C/C++/System C is a plus.
        Modern Verification experience, random techniques, reference models etc.
        Verification of large scale ASICs.
        Verification in chip/SOC/system level.
        Hands-on experience on Object Oriented verification such as UVM/OVM.
        Understanding of simulators.
        Strong cooperation skill with global team.
        Experience of tape-out using 28nm or advanced technology is plus
        Strong self-motivation
        Be open minded, passion and strong drive.
        Excellent team work is required.

sivilar

楼主在此，提醒一下，简历请发送中英文两份，英文简历是必须的。

sivilar

楼主在此，由于级别低没权限回复站短，有提问直接发我邮箱即可。
有版友问是哪个部门招后端和验证，这里统一回复一下，是switching部门

sivilar

自己擦亮一下自己的贴，后端和验证的小伙伴看过来～

sivilar

再次来擦亮擦亮,小伙伴看过来.依然有空缺在哟~

zzj0329

待遇怎么样啊

sivilar

回复 6# zzj0329

待遇看你的水平和申请岗位的级别，反正上海那几个美资企业，互相之间薪资也算是心知肚明啊