cross coverage

yuanpin318

systemverilog中，cross coverage的问题

cp_cmd: coverpoint cmd {
    bins write = {3'b001};
    bins read = {3'b010};
}

cp_address: coverpoint address {
    bins low_mem = {[0:6'h0_1FFFF]};
    bins mid_mem = {[6'h2_0000: 6'h2_FFFF]};
    bins high_mem = {【6’h3_0000: 6'h3_FFFF]};
}

xp_write_low_mem: cross cp_cmd, cp_address {
    bins write_low_mem = binsof(cp_cmd.write) && binsof(cp_address.low_mem);
}

觉得这样写readability 比较好，结果vcs的coverage report中xp_write_low_mem有一个user defined bin, 还有很多autogenerate bin.

有么没有办法disable auto generated bin 而不用ignore_bins的写法?