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属于内部推荐 ， 数字后端 junior 到 staff 都需要
design verfication junior 到manager 都需要。
简历可发 ： chinaxdwl@163.com
具体 JD ：
Physical Design Engineer
Department: SNDS
Primary Location : China-Shanghai-Shanghai
Job: Engineering - Hardware
Description
1. Implementing from Synthesis to GDSII that includes synthesis/DFT implement and check/P&R/ timing signoff and physical signoff
2.Cooperate with colleagues on power fixing based on power analysis result
3.Develop methodologies to make daily work more efficient
4.Cooperate with designers on RTL issues which relative to backend timing closure and congestion solve.
5.Debugging the flow and completion it.
Qualifications
1.BS/MS+ in EE/CS required
2.Have DRC/LVS/ERC/Antenna debugging skills
3.Knows Synopsys /Cadence place-and-route tool set and physical design project implementation.
4.Good programming skill.
5.Capable of writing Tcl or Perl.
6.Familiar with synthesis, static timing analysis is an advantage.
7.Familiar with RTL Design in Verilog is an advantage..
8.Self-motivated team worker, good verbal and written communication skills in English.
Design Verification
Marvell Switching Chip Design team delivers industry leading high performance switching products that serve the data center networking and connectivity. You'll be working with the global team on Switching chip development, driving and manage subsystem/Chip level verification, and provide deployment support to various global products and teams
Responsibility:
？ Work with architecture and designers to get a full deep insight on the design under verification.
？ Subsystem/Chip level state of the art verification, test bench setup/maintain and methodology deployment
？ Test case creation to ensure coding coverage meet target
？ Provide clear status of chip verification progress and issues to management.
Job Requirements:
Education& Qualifications:
？ Candidate is preferred to be MSEE with minimum of 1+ year, or BSEE with minimum of 3+ -year experience in digital ASIC/SOC design verification.
？ Can helping manager to execute plans in project with high quality results
Experience:
？ This is for entry level design verification position
？ Has learnt knowledge of Verilog/C/C++/System C/SystemVerilog.
？ Verification of large scale ASICs.
？ Can understand on Object Oriented verification such as UVM/OVM.
？ Knowledge of low-power design technique and implementation flow is plus.
？ Strong cooperation skill with global team with good oral in english
？ Strong self-motivation
？ Be open minded, passion and strong drive.
？ Excellent team work is required. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2017-6-28 19:30:01
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