【英伟达上海招聘】ASIC PD

Nvidia_Staffing

职位level和salary均开放，投递邮箱：nahu@nvidia.com

We are nowlooking for an ASIC PD EngineerWhat you’ll be doing:

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Chip integrationand netlist generation

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Synthesis

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Netlist qualitycheck

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Formal Verification

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Constraintscreation and validation, timing budget.

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Co-work with PRengineers to implement chip partition and floorplan

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Work in conjunctionwith RR engineers to achieve timing closure for both partition and full chiplevel

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Achieve specialtiming closure, such as io, test, clock etc.

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Function ecocreation

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Develop and enhanceentire timing closure flow from frontend (pre-layout) to backend (post-layout)

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Flow automationdevelopment

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Methodology in anyof above areas.

What we need to see:

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BSEE, MSEE ispreferred

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Project experiencein IC design implementation

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Courses taken incircuit design, digital design

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Hand-on experiencein EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferred

Ways to stand out from the crowd:

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Proficient user ofPerl or TCL is preferred

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Excellent Englishcommunication skill