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- `timescale 1ns/1ps
- `include "uvm_pkg.sv"
- module top_tb;
- import uvm_pkg::*;
- `include "uvm_macros.svh"
- reg clk;
- reg rst_n;
- reg[7:0] rxd;
- reg rx_dv;
- wire[7:0] txd;
- wire tx_en;
- class my_driver extends uvm_driver;
- function new(string name = "my_driver", uvm_component parent = null);
- super.new(name, parent);
- endfunction
- extern virtual task main_phase(uvm_phase phase);
-
- endclass
- task my_driver::main_phase(uvm_phase phase);
- top_tb.rxd <= 8'b0;
- top_tb.rx_dv <= 1'b0;
- while(top_tb.rst_n)
- @(posedge top_tb.clk);
- for(int i = 0; i < 256; i++)begin
- @(posedge top_tb.clk);
- top_tb.rxd <= $urandom_range(0, 255);
- top_tb.rx_dv <= 1'b1;
- `uvm_info("my_driver", "data is drived", UVM_LOW)
- end
- @(posedge top_tb.clk);
- top_tb.rx_dv <= 1'b0;
- endtask
- dut my_dut(.clk(clk),
- .rst_n(rst_n),
- .rxd(rxd),
- .rx_dv(rx_dv),
- .txd(txd),
- .tx_en(tx_en));
- initial begin
- my_driver drv;
- drv = new("drv", null);
- drv.main_phase(null);
- // $finish();
- // rxd = 200;
- // rx_dv = 0;
- // @(posedge rst_n);
- // rxd = 255;
- // rx_dv = 1;
- end
- initial begin
- clk = 0;
- forever begin
- #100 clk = ~clk;
- end
- end
- initial begin
- rst_n = 1'b0;
- #1000;
- rst_n = 1'b1;
- end
- endmodule
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我将上面这个类定义在内部的时候可以正常仿真为什么我单独定义的时候就不能使用了呢?
- `ifndef MY_DRIVER__SV
- `define MY_DRIVER__SV
- class my_driver extends uvm_driver;
- function new(string name = "my_driver", uvm_component parent = null);
- super.new(name, parent);
- endfunction
- extern virtual task main_phase(uvm_phase phase);
- endclass
- task my_driver::main_phase(uvm_phase phase);
- top_tb.rxd <= 8'b0;
- top_tb.rx_dv <= 1'b0;
- while(!top_tb.rst_n)
- @(posedge top_tb.clk);
- for(int i = 0; i < 256; i++)begin
- @(posedge top_tb.clk);
- top_tb.rxd <= $urandom_range(0, 255);
- top_tb.rx_dv <= 1'b1;
- `uvm_info("my_driver", "data is drived", UVM_LOW)
- end
- @(posedge top_tb.clk);
- top_tb.rx_dv <= 1'b0;
- endtask
- `endif
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我使用的是linux环境,questasim10.3a。do文件如下:
- set UVM_DPI_HOME /opt/mentor_graphics/questa/10.3a/questasim/uvm-1.1d/linux_x86_64
- vlib work
- vmap work
- vlog +incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF top_tb.sv
- vlog +incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF dut.sv
- vlog +incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF my_driver.sv
- vsim -ldflags "-lregex" -t 1ns -c -sv_lib $UVM_DPI_HOME/uvm_dpi -voptargs=+acc -L lpm_ver -L altera_mf_ver -L altera_ver -L stratixv_ver work.top_tb
- set StdArithNoWarnings 1
- set NumericStdNoWarnings 1
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