Memory Modeling Portfolio engineer存储设计

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NO.73-【猎头职位：上海需要一位  Memory Modeling Portfolio engineer存储设计】联系人：Shinely-Li,邮箱：hr.@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

PositionDescription:

Ø  Responsible for scheduling,designing, developing, and supporting IP models of system level memory such asSDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFSmodels for use on hardware based verification products. Also responsible forupdating, maintaining, documenting, and supporting existing system level memorymodel products. Perform as individual contributor for RTL design, verification,productizing, and documentation of memory IP.

  Position Requirements:

Ø  The position requires BSEE, orequivalent, with a minimum of 4 years of industry experience in designinghardware systems. RTL design knowledge using Verilog/System Verilog is requiredalong with experience using RTL verification tools and flows. Debugging experience.Experience with team-wide collaboration tools and process.

福利：美资13薪+bonus+五险公司缴纳+股票