Virtuoso AMS混仿导入Schematic后Failed to Simulate的问题

mr_possible

版上的各位大大们好，小弟初来乍到。最近在做一个SAR ADC的仿真，先是用的Verilog-a跑的仿真，到这里都一切正常。然后确认function没有问题了之后，我尝试把其中几个block换成schematic的再仿。我有更新ams的library list，也有重新配置我的config，摁下“RUN”之后，netlist generate没问题，Compile没问题，Elaboration也没问题，然后就报“Failed to Simulate”了，Log文件里也没提及具体是什么问题。我把log file粘到下边了。如有哪位大大知道可能是什么原因造成的问题，还望不吝赐教。先行谢过了！

Log File:


module SAR_ADC_Veriloga.sha:veriloga (up-to-date)

errors: 0, warnings: 0
ncvlog: Memory Usage - 9.7M program + 19.3M data = 29.0M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 92.1% cpu)
Successfully compiled ('SAR_ADC_Veriloga' 'sha' 'veriloga').
ncvlog(64): 08.20-s019: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
file: /home/eng/j/jxf141030/gf65lpe/SAR_ADC_Veriloga/combine_test/schematic/verilog.vams

module SAR_ADC_Veriloga.combine_test:schematic (up-to-date)

errors: 0, warnings: 0
ncvlog: Memory Usage - 9.7M program + 19.3M data = 28.9M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 38.9% cpu)
Successfully compiled ('SAR_ADC_Veriloga' 'combine_test' 'schematic').
Compilation successful.
ncelab(64): 08.20-s019: (c) Copyright 1995-2009 Cadence Design Systems, Inc.

Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
"/proj/cad/library/mosis/GF65_LPe/EDA-CAD-65N-DK012_rev3/ch65lpe_alt_DK012_OA_Rev3/6_00_01_00_LB/ch65lpe_alt/../models/YI-SM00034/1C/sm00034-1c.scs", line 39:

Illegal library definition found in netlist


Discipline resolution Pass...

Building instance overlay tables: .................... Done

Loading native compiled code:     .................... Done

Building instance specific data structures.

Design hierarchy summary:

                 Instances  Unique

Modules:                26       9

Registers:              30      10

Scalar wires:           13       -

Expanded wires:          8       1

Vectored wires:          4       -

Always blocks:          29       9

Initial blocks:         12       2

Cont. assignments:      11       3

Interconnect:           33       -

Simulation timescale:  1ps

Equivalent connect instance summary:

1: combine_test.I17

2: combine_test.I13

3: combine_test.I12

4: combine_test.I11

5: combine_test.I10

6: combine_test.I9

7: combine_test.I8

8: combine_test.I7

9: combine_test.I6

10: combine_test.I16

11: combine_test.I15

12: combine_test.I14

Writing initial simulation snapshot: SAR_ADC_Veriloga.combine_test:config

Elaborating analog portion of the design hierarchy:

libsyracuse:  @(#)$CDS: libsyracuse version   11/15/2009 22:11 (chfclx007) $(sub-version  1115  )
ncelab: Memory Usage - 24.1M program + 756.2M data = 780.3M total
ncelab: CPU Usage - 0.3s system + 1.3s user = 1.6s total (3.9s, 40.4% cpu)
Successfully elaborated ("SAR_ADC_Veriloga" "combine_test" "config").
ncsim(64): 08.20-s019: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
Failed to simulate ("SAR_ADC_Veriloga" "combine_test" "config").
txe(64): 08.20-s019: (c) Copyright 1995-2008 Cadence Design Systems, Inc.

mr_possible

要把所有仿真的模块放到同一Lib下就没问题了...分开几个Library哪怕在cell bingings里都设置好也是无法仿真的...也不报个错...

hustjzr

你好，楼主，最近我在学习virtuoso 6.1.7的Verilog-A仿真，在写完Verilog-A代码后，check时一直报warrning，后面仿真也无法继续，请问有遇到过这种问题吗

paji

学习中