11.1 An Oversampled 12/14b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.1dB SNDR
11.2 A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS
11.3 A 10b 0.6nW SAR ADC with Data-Dependent Energy Savings Using LSB-First Successive Approximation
11.4 A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SAR-Assisted Pipelined ADC in 28nm CMOS
11.5 A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using Self-Biased Ring Amplifiers
11.6 A 21mW 15b 48MS/s Zero-Crossing Pipeline ADC in 0.13μm CMOS with 74dB SNDR
11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz
22.1 A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS
22.2 A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
22.3 A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology
22.4 A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with 10:15 AM Background Timing-Skew Calibration
22.5 A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS
22.6 A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers
22.7 A 14b 4.6GS/s RF DAC in 0.18μm CMOS for Cable Head-End Systems 2014.part1.rar(14.31 MB, 下载次数: 657 )
2015压缩包里面具体文献名称为：
3.6 A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm CMOS
Session 15 Overview: Data-Converter Techniques
15.1 An 85dB-DR 74.6dB-SNDR 50MHz-BW CT MASH ΔΣ Modulator in 28nm CMOS
15.2 A 4.5mW CT Self-Coupled ΔΣ Modulator with 2.2MHz BW and 90.4dB SNDR Using Residual ELD Compensation
15.3 A 115dB-DR Audio DAC with –61dBFS Out-of-Band Noise
15.4 A 0.8V 10b 80kS/s SAR ADC with Duty-Cycled Reference Generation
15.5 A 0.6V 1.17ps PVT-Tolerant and Synthesizable Time-to-Digital Converter Using Stochastic Phase Interpolation with 16× Spatial Redundancy in 14nm FinFET Technology
15.6 A 12b 250MS/s Pipelined ADC with Virtual Ground Reference Buffers
15.7 A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS
15.8 A 90dB-SFDR 14b 500MS/s BiCMOS Switched-Current Pipelined ADC
26.1 A 1mW 71.5dB SNDR 50MS/s 13b Fully Differential Ring-Amplifier-Based SAR-Assisted Pipeline ADC
26.2 A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC Utilizing a Redundancy-Facilitated Background Error-Detection-and-Correction Scheme
26.3 An 800MS/s 10b/13b Receiver for 10GBASE-T Ethernet in 28nm CMOS
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS
26.5 A 5.5mW 6b 5GS/s 4×-Interleaved 3b/cycle SAR ADC in 65nm CMOS
26.6 A 5GS/s 150mW 10b SHA-Less Pipelined/SAR Hybrid ADC in 28nm CMOS
26.7 A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4×-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique
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发表于 2017-4-4 16:50:27
