具体文献名称如下：
16.1 A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC
16.2 A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving -161dBFS/Hz NSD
16.3 A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration
16.5 An 8GS/s Time-Interleaved SAR ADC with Unresolved Decision Detection Achieving -58dBFS Noise and 4GHz Bandwidth in 28nm CMOS
16.6 A 10b DC-to-20GHz Multiple-Return-to-Zero DAC with >48dB SFDR
16.7 A 12b 10GS/s Interleaved Pipeline ADC in 28nm CMOS Technology
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter
28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT Delta-Sigma Modulator Using 6b Double-Noise-Shaped Quantizer
28.3 A 125MHz-BW 71.9dB-SNDR VCO-Based CT ΔΣ ADC with Segmented Phase-Domain ELD Compensation in 16nm CMOS
28.4 A 12b 330MSs Pipelined-SAR ADC with PVT-Stabilized Dynamic Amplifier Achieving 1dB SNDR Variation
28.5 A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
28.6 A 78.5dB-SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating up to 75MS/s with 24.9mW Power Consumption in 65nm CMOS
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique 2017.part1.rar(14.31 MB, 下载次数: 609 )
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发表于 2017-4-4 16:21:50
