【AMD社招】Design Verification Engineer

RecruiterAMD

AMD超威半导体上海研发中心招聘 ASIC Design Verification Engineer；请有意向者将简
历发送到 Maggie1.Zhang@amd.com 以及 Cherry.Zhang@amd.com


Job Location: Shanghai


Job description:

We are currently looking for engineer who will be responsible for design verif
ication of cutting edge GPU projects. Qualified candidate will participate in
and lead SoC level function verification domains including:

1.    SoC DV testbench and infrastructure development and maintenance

2.    Create and execute SoC testplan including data-path and interrupt, virtu
alization, security, power management, etc.

3.    Implement directed and random test cases in C++/SV, as well as checkers

and assertions

4.    Support integration and qualification of all the IPs for SoC

5.    Help to improve DV environment building flow



Requirement:

-   MS with 7+ or BS with 9+ years’ experience in ASIC/SoC design verification

-   DV lead experience is a must

-   Hand-on experience in all domains of complex ASIC DV flow from plan to cov
erage, both

-   Knowledgeable in C++ & SV development, familiar with scripting languages l
ike Ruby/Perl/Makefile…

-   Strong problem solving and communication skills

-   Knowledge on computer architecture and PCIe devices is highly preferred

-   Good knowledge on verification methodologies like UVM is a big plus

-   Experience in power-aware verification is an asset