IC617 spectre仿真问题（新版.def文件需要用verilog-A文件代替问题）

hutushenxinxin

各位大大，我在运行电路原理图仿真时，出现以下错误，求解决！！

Fatal error found byspectre during Ahdl read-in.

         FATAL (VACOMP-2096): File ‘/home/kx/Myproject/kx_test2/smic13mmrf__1225_1P8M_2000605271040/models/spectre/res_rf.def’ does not appear to be a vaild verilog-Afile. In previous release, ‘.def’ was a file extension typically used forSpectreHDL files but SpectreHDL is no longer supported. If this file isSpectreHDL file. You need to replaced it with an equivalent Verilog-A file.

请问这种解决办法是使用verilog-A文件更换.def文件吗？如果是求哪位大大发我一个verilog-A文件，跪求。如果不是，需要怎么修改呢？

模拟电路入门者

同秋