在线咨询 切换到宽版
eetop公众号 创芯大讲堂 创芯人才网

 找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

搜全文
查看: 1226|回复: 0

[招聘] 【AMD全职】ASIC Design Verification Engineer

[复制链接]
发表于 2017-3-9 15:24:09 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
AMD 热招前端验证工程师,福利优厚,机会多多!欢迎各位有意者发送简历或推荐朋友至Ciela.Wang@amd.com 标题注明应聘职位。Sr/MTS ASIC Design Verification EngineerJob Location: ShanghaiJob description:We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:1.         SoC DV testbench and infrastructure development and maintenance2.         Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.3.         Implement directed and random test cases in C++/SV, as well as checkers and assertions4.         Support integration and qualification of all the IPs for SoC5.         Help to improve DV environment building flow Requirement:-   MS with 3/5or BS with 5/7 years’ experience in ASIC/SoC design verification-   DV lead experience is a must-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both-   Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…-   Strong problem solving and communication skills-   Knowledge on computer architecture and PCIe devices is highly preferred-   Good knowledge on verification methodologies like UVM is a big plus-   Experience in power-aware verification is an asse
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

手机版| 小黑屋| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-9-17 04:03 , Processed in 0.010866 second(s), 4 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表