【Cadence 上海+深圳】招Principal Hardware Based Design and Verification Engineer

kengteng

投递方式：

If you have interest , PLS send your update CV to job_china@cadence.com(简历投递格式：姓名+学校+申请职位+工作地点)

Location: 上海&深圳

Sr. Staff /Principal HardwareBased Design and Verification Engineering

Position Description:

He/she will lead and be a participating member of a team ofadvanced field engineers who deploy and support advanced hardware basedverification flow integration technical engagements and provide easy-to-adoptpackages and workshops to Cadence field application engineers and customersalike.

He/she will focus on the technical aspects of the followinghardware verification solutions for customer engagements as well as creatingdemos/workshops to train field AE and customers:

(1) Cadence Palladium HW Acceleration Platforms

(2) Cadence Acceleratable Verification IP portfolio

(3) HSV product integration with other Cadence products suchas Incisive Simulation and/or Joules for power analysis

(4) HW/SW Co-verification solutions for SoC designs

The person must be a strong team leader and contributor,leading projects and initiatives for the local regions and maintain a strongconnection with the US team. He/She must be able to travel and coach AEs amongAP regions for multiple engagements.

HW based verification experience such as other emulators orFPGA prototyping based verification is required

Expertise in RTL top-down design and verificationmethodology automation are required. This includes full hands on knowledge ofwriting and debugging Verilog, VHDL and SystemVerilog based D&Venvironments.

We would also like the candidate to have good knowledge ofSoC design principles, embedded software development and HW/SW co-design andco-verification.

The person should possess team-success orientation, maturework attitude, and good judgment under pressure.

PositionRequirements:

- Minimum Education Required: education level of BS with 12+years’ experience (or MS with 10+ or more years’ experience).

- A good knowledge of RTL design and verification tools(HDLs, synthesis tools, design simulation, acceleration using emulators)

- Knowledge of the needs of SoC design and verification

- Knowledge of UNIX, C/C++, other scripting programminglanguages (Perl, TCL…) is highly desired

- Strong verbal and written communication skills in Englishare required

- At least 12+ years’ experience in the following areas:

- HWacceleration or In-Circuit Emulation or FPGA prototyping experience is a must

  - Hardware verification, including knowledgeof HDL simulators and debugging simulations

  - Hands on experience with using design andverification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is amust.

  - Knowledge ofembedded systems and software development for SoCs is a plus