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AMD超威半导体上海研发中心招聘 Sr. /MTS Engineer for Front-End integration;请有
意向者将简历发送到 Maggie1.Zhang@amd.com 以及 Cherry.Zhang@amd.com
Responsibility:
o Integrate functional IPs into SoC per architectural requirement.
o Develop RTL code for macro blocks in Verilog HDL and make sure functional co
rrect and reusable for different configuration.
o Participate in making functional/technology based chip targets in timing, ar
ea, power. Develop timing constraint, power intent spec accordingly.
o Synthesis and deliver qualified netlist, cowork with PD to settle chip floor
plan and achieve timing closure.
Requirement:
o Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+
years working experiences in ASIC Company.
o Familiar with one or more ASIC flows (logic synthesis, STA, formality check,
Design for Power ) and usage of related EDA tools.
o Familiar with script languages ((tcl, perl etc.) in unix/linux.
o Familiar with IO analog macro knowledge is a plus
o Good problem solving and communication skills
o Good written and spoken English.
o Good communication skills and be able to work both independently and in a team. |
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