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I have a module, there is not a clock pin to/from the module, but one sub-module generates quite a few clocksignals, as low as 10MHz, but as high as 5GHz, to the other sub-modules.
Please help:
1) how do I handle those internal clock signals in design compiler?
2) the module was synthesized hierarchically as whole, without any constraints for those clocks, should I go back
synthesize them, those receiving those high speed clocks one by one? |
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发表于 2017-2-9 00:59:23
