成都Marvell招聘IC Physical Design engineer

kobefly225

Description

• Logic     synthesis: including memory replacement, RTL sanity check, std. cell     mapping, timing, power, and area optimization, scan stitching, formal     verification and signoff.
• Design     for test: including DFT spec and partition, BSD/JTAG/MBIST logic     generation and insertion, scan chain insertion and pattern generation,     simulation and verification, DFT SDC file deliver.
• Physical     implementation: including floorplan, power routing, placement, clock tree     synthesis, timing closure, routing, si fixing, drc fixing, dfm ...etc
• Physical     verification: including low power check, timing analysis, timing eco,     xtalk analysis, power analysis, ESD analysis, EM analysis, drc check, lvs     check, ant check, erc check ...etc
• Tapeout:     timing signoff, power signoff, design tapeout... etc

Qualifications

• BS/MS     in EE, CS major in VLSI, logic or CPU design.  Good GPA required. Or     1-3 years of hands-on experience in IC design industry
• Hands-on     experience in IC design industry or in college is preferred.
• Detail     oriented, self-motivated and team player.  Good verbal and written     communication skills.
• To     qualify for the job, you should have some or all of the following     technical background:

a.   Working knowledge of HDL, such as Verilog , frontend design or SOC integrationexperience, including synthesis, timing analysis, timing constraint creation,and

                      formal verification.  Experience in Design-for-test (DFT), with JTAG, BISTand SCAN.  

b.    Working knowledge of LEF/DEF andbackend physical design, such as floorplanning, standard cell placementand routing or layout integration.

c.    Understandingof SPICE model and transistor circuits, and standard cell layouts.

   d.    IC design methodologies using design automation EDA tools,ASIC design flow, and deep sub-micron technology issues.

   e.    Familiarization with scripting programming, such as Tcl orPerl.  Experience with makefile and understanding of the design automationfor efficiency.

    f.    Working experience with any of the EDA tools listed below:

                     i.         Synopsys:  IC Compiler,StartRC, PrimeTime, PT-SI, PrimeRail, Formality,  Hercules, DesignCompiler, TetraMAX)

                      ii.         Cadence:  EDI, SOCEncounter, Nanoroute, Celtic, Verplex, RC

                      iii.        Magma: Talus, Blast

                      iv.        Mentor: Calibre, TestKompress,FastScan, MBIST, BSD

                      v.         Ansys: Apache Redhawk

Please send resume to mailbox(gxfeng@marvell.com) if you have intention, thank you!

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   高新区 天府软件园

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   天府软件园 C区