abstract:
This work presents cirsuit-level simulation and layout optimization techniques for a multifinger NMOS device. By considering the full thermal-coupling of heat sources at each drain finger,simulation reflect the device layout depent behaviour in silicon under EOS/ESD, simulation reveals that each NMOS finger many carry a different stress current due to the total NMOS width will be reduced. simulation results agree well with measured data. we also proposed s design and layout optomization methodology which is illustrated with a design example.
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发表于 2007-6-12 12:34:44
