Cadence 北京招聘Principal/Lead Design Engineer

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Cadence 北京招聘Principal/Lead Design Engineer， 有意者请将简历发至541515639@qq.com, 标题中请注明应聘职位。

Position Description:

 Cadence/Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible for verification of advanced DSP cores and their instruction set architectures and hardware implementations. You will implement architectural simulation test benches in C/C++/RTL, write C/assembly language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test plans, debugging failures and analyzing coverage information. You will work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.


Position Requirements:
 Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processor architecture concepts
 Good knowledge of C (C++ will be a plus)
 Working knowledge of Verilog and popular EDA simulators and testbench methodologies
 Knowledge of scripting languages such as Makefile/Perl is desired
 Knowledge of assembly programming and programming in a high level language such as C
 Good English communication skills – both written and verbal
 Strong problem solving skills along with an ability to work independently and in cooperation with global teams
 MS degree in EE/CS with 3 to 5 years industry experience required.

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tonglvyi

very good

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