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地点:武汉
企业:Synopsys (新思科技) - 美资企业
职位:asic Digital Design Engineer (Senior)
待遇:10K-30K/月(具体定级,面谈)
要求:从事ASIC设计相关工作1年以上,具有一般英语口语能力(因为要经常与海外其他团队电话会议)
联系方式:chhuang@synopsys.com(内部推荐)
英文岗位要求描述:
- Strong desire to work with embedded processors or processor based systems · Knowledge of hdl design and ideally, RISC architectures
· Understanding of programming at assembly and C/C++ level
· Understanding of Hardware Verification Methodologies and best practices – Coverage Driven Verification, constrained random testing, VMM, eRM, OVM, UVM
· Understanding of design/verification languages such as, System verilog, Verilog, VHDL, Specman e, Vera
· Knowledge of Perl or other scripting languages for flow automation
注:待遇只做参考,根据面试结果浮动。 |
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