modelsim后仿真网表，rom出现不定态的问题

xiajinminyu

modelsim后仿真网表，rom的信号本来没有问题，后来更改了ROM的初始化数据，ROM的某些信号就出现不定，报的error如下：

#
# 422404584.28 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404638.53 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404692.78 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404747.04 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404801.29 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404855.54 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#
#
# 422404909.79 ns: ERROR: AA_tb_cpu_spi_flash.cpu_spi_flash_filter_u.full_chip_u.cpu_filter_u.boot_rom : CEn is at x at CLK rising edge:
#



，只是换了一组数据而已，各位大侠，为什么会出现不定态，之前那组数据都没有问题的。（已经反标上SDF文件了）。

查看rom的verilog model 有下面这一段：

`ifdef ATPG_RUN
`else
initial begin

$timeformat (-9, 2, " ns", 0);

rt = 1'b0;

#250 ;
// no ROM activity permitted for first 250ns of sim.

rt = 1'b1;

end
reg last_CLK_;
always @(CLK_)
last_CLK_ <= CLK_;
always @(posedge CLK_)

begin

if (CEn_ === 1'bx)  $display ("\n%t: ERROR: %m : CEn is at %b at CLK rising edge:\n", $realtime, CEn);

if (enableMem === 1'b1)

begin

if ((CLK_ == 1'b1 && last_CLK_ === 1'bx) || (CLK_ === 1'bx && last_CLK_ == 1'b0))

if ($realtime>0.00) $display ("\n%t: ERROR: %m : bad CLK rising edge:\n", $realtime);

end

if(rt === 1'b0)


begin
         
if (CEn_ === 1'b0 ) $display ("\n%t: ERROR: %m : ROM enabled during initial 250ns\n", $realtime);


end

end
`endif


求大神分析一下啊，谢谢！