回复 8# vint019
I have some questions about the LNA standalone design with input and output match to 50Ohm, here is my design flow.
1)
Under power constraints, I just limit the current to 5mA, and I can got the MOS FET width. As I know, gmoverid about 10 if VGS close to the Vth. Then I can got the gm about 50ms.
2)
Inductor Ls provide the resistive part of input impedance. Ls have less relationship with Yopt = Ropt + Xopt, and I can find one Ls and make the input impedance real part Rin equal to the Ropt.
3)
Then I can find one gate inductor Lg, to make the Xopt = X*in(conjugate of image part of input impedance), after the source match to the Rin + j Xin, the noise figure reach to the minimum Nfmin.
4)
Now I just to match the 50Ohm port to the impedacne in step 3), and S11 now is matched.
Question:
1)
if make LNA output match to 50Ohm, find the S12< -35dB, reverse isolation is good, but output match still affect input, how to make output and input match to 50 at the same time?
2)
In real engineering design, what’s the design start point? NF? Gain or current?
3)
What time to check the stability factor KF and B1f? I find is use the ideal Ld to simulate, the circuit sometime unstable. |