别沉了啊
补充一下,用ODDR2时候的时钟产生模块,希望有人能帮我看看,在此先谢过。
`timescale 1ns/1ps
module clk_gen(
input I_rst ,
input I_clk_50 ,
input CLK_OUT3_CE ,
output O_clk_out
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (I_clk_50));
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKIN_PERIOD (20.0),
.CLKOUT3_DIVIDE (100),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
pll_base_inst
( // Output clocks
.CLKFBOUT (clkfbout_buf),
.CLKOUT0 (),
.CLKOUT1 (),
.CLKOUT2 (),
.CLKOUT3 (clkout3),
.CLKOUT4 (),
.CLKOUT5 (),
// Status and control signals
.LOCKED (),
.RST (I_rst),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1)
);
BUFGCE clkout3_buf(
.O (W_clk_out),
.CE (CLK_OUT3_CE),
.I (clkout3)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(O_clk_out), // 1-bit DDR output data
.C0(W_clk_out), // 1-bit clock input
.C1(~W_clk_out), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule |