模拟版图 memory 版图

jj_seu

Analog Circuit Layout Design Engineer（Serdes Layout）@上海
北京

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

Description:

1. Full custome analog layout/verificationand RC extraction.

2. Perform block level layout. Conductphysical verification (DRC and LVS using Cadence tools).

3. Team work with analog designers,optimize layout.

Qualification:

1. Bachelor or above degree with N yearsexperiences in CMOS IC full-custom layout.

2. Experiences in Mixed signal/analog/highspeed layout，SerDes、ADDA、PLL，etc.

3. Familliar with layout skills andknowledge is must.

4. Good teamwork/communication/positive ismust.

5. Familiar with Cadence IC layout andverification tools

6. Having massive IP block experience

7. Familiar with 0.18/0.13/0.09/0.065/0.04um CMOS process and design rule is a plus.

8. Familiar with ESD/Latch up/antenna andrelated layout solutions is a plus.

9. Familiar with rule deck is a plus.

模拟版图Layout@上海
北京

简历发芯得 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]      

职位描述：

1. 基于CMOS模拟IC的版图设计，负责模块或者整个芯片的布局规划、版图绘制、验证优化

2. 主要涉及 SerDes、ADDA、PLL等领域

岗位要求：

1 微电子类相关专业，熟悉linux

2  N年(以上更好)模拟版图设计经验，熟悉芯片制造流程

3 熟练使用 Virtuoso/Laker/Calibre 等软件

4 有良好的团队合作精神，开放的学习态度

有以下经验优先考虑

4 熟悉 LVS、DRC、PERC 等rule 编写

5 熟悉shell、perl、tcl、python等脚本语言

6 良好的英语沟通能力

7 TSMC、SMIC 工作经验，熟悉工艺

备注

1）工作年限：Analog领域3年以上

2）相关经验：侧重serdes, PLL, ADC/DAC,Memory 的经验

3） 工艺要求：侧重小工艺，如65/45/32/28等等。

Memory Layout@上海
北京
深圳
简历发 hr@hi-talent.com     

1.    Physical Design forMemory Products: Full custom Layout for analog and digital circuits in High performanceDRAMs.

2.    Floor planning signal-and bus planning according to predefined specifications.

3.    Chip sizeoptimization.

4.    Area- and parasiticoptimized layout.

5.    Assembly of BLKs andtop level hierarchies including routing.

6.    Verification ofcircuits (Design Rule Check, Layout versus Schematic, Electrical rule check).

7.    Generation of fillstructures according to technology requirements.

8.    Optical simulations ontechnology driven circuits.

9.    Investigations onElectro migration and IR drop.

Requirements:

1.    Bachelor inMicroelectronics, Electronic Engineering, or related field.

2.    Familiar with CADsoftware.

3.    Familiar withsemiconductor process and structures of devices.

4.    Team oriented, love towork in young, international and highly motivated teams.

5.    Good communicationskills.

6.    High grade offlexibility.

7.    Highly motivated andengaged.

8.    Experience in digitalanalog and or mixture signal IC is preferred.

9.    Experience inFlash,SRAM and DRAM design is preferred.

10.  Experience in backend design flow(APR) is preferred.

11.  English language skill in writingand speaking is a must.

Memory layout designer@上海
北京
深圳
简历发 hr@hi-talent.com

全定制版图设计者，根据各种模拟电路或者存储器电路进行版图设计，并通过各种物理验证和各种细节检查，然后制作报告书。

岗位要求:

大专及以上学历，集成电路或微电子或电子等相关专业；

熟悉集成电路设计流程，2年以上模拟或者存储器版图设计经验；

精通Linux操作系统，熟悉cshell或者perk/awk语言等，精通其中一项语言者有加分；

能够熟练使用laker和virtuoso软件制作版图，能够熟练使用calibre或者hercules进行DRC,LVS等相关验证，精通tcl或者skill语言者有加分；

具备阅读各种英文设计资料的英语水平；

备注：画SRAM IP，有过memory layout经验，包括DRAM, flash等都可以，但有32nm以下小尺寸版图经验者优先

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

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