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有人用过Xilinx 以太网 1G PCS/PMA 或 SGMII IP LogiCORE™吗？ 本人在使用的时候gt0_qplloutclk，gt0_qplloutrefclk两个时钟一直不输出，这两个时钟是transceiver的时钟，，下面给的是他例子里使用gtex2_common的源语生成那两个时钟的程序，我用ISIM仿真的时候都有，但是引到外部管脚上就测不到，跪求大神指点如何生成这两个时钟
`timescale 1ns / 1ps
`define DLY #1
//***********************************Entity Declaration************************
module gmii2sfp_gt_common
(
input gt0_gtrefclk0_common_in,
output gt0_qplloutclk,
output gt0_qplloutrefclk,
output gt0_qplllock_out,
input gt0_qplllockdetclk_in,
output gt0_qpllrefclklost_out,
input gt0_qpllreset_in
);
//***************************** localparam Declarations ************************
localparam QPLL_FBDIV_TOP = 16;
localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
localparam WRAPPER_SIM_GTRESET_SPEEDUP = "FALSE";
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
//_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("4.0"),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (gt0_gtrefclk0_common_in),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports -----------------------
.QPLLDMONITOR (),
//--------------------- Common Block - Clocking Ports ----------------------
.QPLLOUTCLK (gt0_qplloutclk),
.QPLLOUTREFCLK (gt0_qplloutrefclk),
.REFCLKOUTMONITOR (),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (gt0_qplllock_out),
.QPLLLOCKDETCLK (gt0_qplllockdetclk_in),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (gt0_qpllrefclklost_out),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (gt0_qpllreset_in),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
//------------------------------- QPLL Ports -------------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b11111),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule |
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发表于 2016-6-23 09:03:34
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