模拟+版图+验证简历发 ic@hi-talent.com

jj_seu · 发表于 2016-6-14 16:00:49

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模拟 +版图+验证芯得经典case 简历发 hr@hi-talent.com

Analog Design Engineer 简历发 芯得 hr@hi-talent.com

Location: Shanghai, Beijing

Responsibilities:

芯得客户 Analog Design Engineer is working on cutting-edge Analog and Mixed-signal IP development for 芯得客户 worldwide clients, including High Speed Serial Links, PLL, ADC/DAC, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the definition, design, layout, and characterization of the analog and mixed-signal circuits.

Requirements:

1. ME/EE or background in related areas.

2. At least 2 years industry analog design or verification experience.

3. Able to design circuits that operate effectively within the process window, and supervise layout floorplan and design.

4. Demonstrate good knowledge and experience in advanced analog and mixed-signal circuit design, experience in one or more of the following circuits, is a plus:

• Driver / Receiver

• Serializer / Deserializer

• Phase Interpolator

• VCO, Charge Pump, Clock Divider, PFD

• Bias, Bandgap, Voltage Regulators

5. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.).

6. Good understanding of advanced semiconductor technology process and device physics.

7. Experience with system level modeling and simulation by MATLAB, Verilog-A or C/C++ is a plus.

8. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.

9. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

Layout Design Engineer 简历发 芯得 HR@hi-talent.com

Location: Shanghai/Beijing

Responsibilities:

芯得客户 is looking for a strong technical leader and design engineers to join our world-class Layout team! Circuit Layout Engineers at 芯得客户 are responsible for creating circuit layouts (analog custom logic, mixed signal) for our industry-leading SerDes offering. The ideal candidate will have extensive experience with the layout of analog and some high speed custom digital circuits for High Speed Serial IO Interfaces in ASIC applications. Applicants must have several years of experience in this area must have experience using the design tools associated with these tasks, preferably Cadence tools, and must be familiar with current CMOS technology generations (32nm and below). The layout engineer will direct the floor planning, lead other layout designers with leaf cell and block creation, and integration of analog blocks within the IP block. The person should be familiar with learning new tools, methodologies, and technology. Applicants must be good team players. Knowledge and/or experience with Serial Link applications is a significant plus. Graduate level education with an emphasis in analog circuit design is preferred.

Requirements:

1. BS in Electrical or Computer Engineering.

2. At least 5 years full-custom analog layout/verification and RC extraction experience.

3. Experiences in Mixed signal/analog/high speed layout，SerDes、AD-DA、PLL，etc.

4. Deep Experience with layout in the Cadence Design Environment. Familiar with Virtuoso XL and physical verification tools (DRC,LVS,DFM,YCD,etc).

5. Experienced with Electro migration and voltage drop analysis.

6. Ability to recognize critical signal nets and reduce parasitics by proper floorplanning/placement

7. Good understanding of advanced semiconductor technology process and device physics.

8. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.

9. Good English skills, communication skills, and willingness to work with a global team.

10. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

Logic Verification Engineer 简历发 芯得 hr@hi-talent.com

Location: Shanghai, Beijing

Responsibilities:

芯得客户 Logic Verification Engineer is working on cutting-edge Digital and Mixed-signal IP development for 芯得客户 worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic verification or mixed signal verification.

Requirements:

1. ME/EE/CS or background in related areas.

2. Research and/or development experience in one or more of the following areas:

• Logic verification on the basis of the target system specification

• Mixed-signal model verification on advanced technologies

• Proficiency in programming and/or scripting languages is a plus

• Knowledge on Protocols, High Speed Serdes or DDR is a plus

3. Experience in one or more of the following application domains, is a plus

• High performance computing system, processor, chipset and ASICs

• High end communication, networking, mobile and data center applications

• Digital signal processing, sensor and Internet of Things

• Other emerging IT technology and industry areas