在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
查看: 2432|回复: 5

[招聘] 科胜讯(成都)设计/验证/后端/ 等多岗位热招

[复制链接]
发表于 2016-5-16 19:43:49 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

美国科胜讯国际有限公司是全球无工厂IC设计公司之一,在众多的市场上,科胜讯已经确立了拥有世界一流客户群的全球领导地位。今天,科胜讯的系统级解决方案已经应用到全世界70%以上的传真机和80%的CDMA电话之中,另外还有60%以上的互联网连接是通过科胜讯的设备实现的。除此之外,科胜讯在卫星电视,数字电视接收机方面提供的半导体产品也占有50%以上市场份额。

公司地址:成都市高新区天府大道天府软件园A区A8幢6楼

近期招聘职位如下,有兴趣的可以发送中英文简历到邮箱:Xiao.Wen@conexant.com

数字验证工程师

成都

Target Candidate:
Experiencd in asic verification.

Minimum Experience: 3+ years

Key Areas of Responsibilities

-Write verification plans according to architecture document

-Writing behavioral models, monitors, and self-checking testbenches

Required Skills and Attributes

-Experience of verilog, SystemVerilog, UVM
-Hands on experience of SOC architecture, micro-processor verification, andsilicon debug environment

高级模拟混合信号设计工程师

成都

Target Candidate:
Experienced CMOS Analog/mixed-signal circuit design
Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Design of high-performance low-power data converters, analogfront-ends and power management blocks.

-Participate in product definition, implementation, verification,and lab validation

Required Skills and Attributes

-Expert knowledge in high resolution sigma-delta A/D and D/Aconverters, Class-D PWM amplifiers, DC/DC converters.

-Expert knowledge in transistor-level analog CMOS designfundamentals, including operational amplifiers, continuous-time anddiscrete-time circuits

-Strong knowledge in signal processing fundamentals

版图工程师       成都

Target Candidate:
Experienced in layout design
Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Analog Mixed Signal Layout Engineer who has extensive experiencein analog circuit layout, ADC, DAC, PLL, PAD etc.

Required Skills and Attributes

-3+ years of mask layout experience working advanced nodes

-3+ years of experience with virtuoso, caliber, etc.

-Full chip DRC and LVS experience

硬件设计工程师             成都

Target Candidate:
Experienced in
Hardware design
Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Write hardware design specification and Design schematicsand
layout.

-Debug and solve any issue during the development

-Audio or acoustic design/integration and tuning to providecompelling end user experience

Required Skills and Attributes

-Hardware design experience on digital and analog circuits

-Be familiar with power supply system, clock system and interfacestandards (I2C, USB, SPI, Bluetooth, I2S, etc.)

-Be familiar with EDA tool Cadence or Mentor
 楼主| 发表于 2016-5-17 12:19:40 | 显示全部楼层
公司不错,管理人性化,自顶一个。
发表于 2016-5-19 14:03:03 | 显示全部楼层
自己顶?
发表于 2016-5-19 15:54:21 | 显示全部楼层
堂堂贵族conexant,现在都成这样了哎。
发表于 2016-5-26 11:50:25 | 显示全部楼层
科胜讯不是听说倒闭了吗?怎么又起来了?
发表于 2016-6-16 19:57:28 | 显示全部楼层
回复 1# wenxiao925


   请问楼主,模拟layout还在招人吗?谢谢
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-5-14 09:01 , Processed in 0.036894 second(s), 8 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表