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发表于 2016-5-11 10:58:48
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JD:
Primary Location
: CHN-Shanghai-Shanghai
Description
Participate in developing highly integrated, high performance and high precision ASSPs for industrial, communication and healthcare markets.
Responsible for digital verification architecture and testbench design by using advanced verification methodologies.
Developing verification automation scripts to improve verification efficiency.
Developing and implementing the test suites, functional coverage, assertions and other metrics to track progress and completeness of verification effort.
Analyzing and debugging the design issues
Working closely with designers to guarantee first pass silicon success
Qualifications
MSEE in EE related majors.
Experiences on digital circuit design with Verilog
System Verilog and/or UVM are a strong plus.
Excellent problem solving skills
Good initiative and motivation in a challenging environment
Strong communication skills
The ability to work well in a team environment and share knowledge and expertise
Good spoken and written English |
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eetop公众号
创芯大讲堂
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发表于 2016-5-10 15:09:33
