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是一个存在存储器中的查找表,查找表高八位是时间,低八位是数值,首先读出第一个数值,延迟高该数值高八位的时间后输出这个数值,然后按顺序读出下一个数值,接着延迟下一个数值高八位时间后输出该数值,依次类推,直到全部输出.小弟刚学verilog,只能写成这样 死活弄不出来,还请各位高手指点一二,万分感谢
module lshiyan(clk,rst,data,tr,addr);
input clk,rst,tr;
input[2:0] addr;
output[4:0] data;
reg[2:0] addr;
reg[4:0] databuf;
reg[4:0] register[7:0];
reg[15:0] stctab[7:0];
reg[7:0] ti;
parameter state_size=3;
parameter IDLE=3'001,stc1=3'010,stc2=3'011,stc3=3'100;
reg[state_size:0] state;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
state<=IDLE;
stctab[0]<=16'd0000000100000001;
stctab[1]<=16'd0000001000000010;
stctab[2]<=16'd0000010000000100;
stctab[3]<=16'd0000100000001000;
stctab[4]<=16'd0001000000010000;
stctab[5]<=16'd0010000000100000;
stctab[6]<=16'd0100000001000000;
stctab[7]<=16'd1000000010000000;
end
else
begin
case(state)
IDLE:
begin
if(tr)
rbuf<=r;
databuf<=register;
ti<=8'b00000000;
addr<=3'b000;
state<=stc1;
end
else
begin
databuf<=databuf;
register<=5'b00000;
ti<=8'b00000000;
addr<=3'b000;
state<=IDLE;
end
stc1:
begin
ti<=stctab[15:8];
stc1<=stc2;
end
stc2:
begin
repeat(ti) @(posedge clk);
register<=stctab[7:0];
stc2<=stc3;
end
stc3:
begin
databuf<=register;
stctab[addr]<=stctab[addr+1];
stc3<=IDLE;
default: state<=IDLE;
endcase
end
assign data=databuf;
endmodule |
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