[Opt 31-67] Problem: A LUT1 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: ac701_pcie_x4_gen2_support_i/inst/inst/gt_top_i/reg_clock_locked_i_1.
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2016-4-6 09:27:12
