Error: (vsim-13) Recompile work.my_if2

wide_road

文件1   my_if2.sv`ifndef MY_IF__SV
`define MY_IF__SV
interface my_if2(input clk, input rst_n);
   logic [7:0] data;
   logic valid;
endinterface
`endif



文件2   my_if2.sv`ifndef MY_IF__SV
`define MY_IF__SV
interface my_if2(input clk, input rst_n);
   logic [7:0] data;
   logic valid;
endinterface
`endif


文件3    top_tb.sv

`timescale 1ns/1ps
`include "uvm_macros.svh"

import uvm_pkg::*;
`include "my_if.sv"
`include "my_if2.sv"
`include "my_driver.sv"

module top_tb;

...
endmodule

报错： Error: (vsim-13) Recompile work.my_if2 because work.top_tb_sv_unit has changed.
Error loading design

解决：
文件2 中的红色文字部分改成：
`ifndef MY_IF2__SV
`define MY_IF2__SV