new test

drysky

经过两天的折腾终于看到功能覆盖率的报告了

                               
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  本人初学，欢迎讨论、批评指正。希望对大家有帮助。

提示一：
covergroup里的option.per_instance一定要设成1（默认是0，不保存覆盖率数据），
option.per_instance = 1;  为了这个调试了两天，cadence的工具也不给个提示。。。
当然也可以在ccf（coverage configuration file）里设置全局的参数，如下：
select_functional
set_covergroup -default_goal 100
set_covergroup -per_instance_default_one

提示二：
仿真命令，希望对大家有帮助

                               
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irun \
-svseed random \
-access +rwc \
-coverage functional \
-covfile cov.ccf \
-uvm \
-uvmhome /home/bill/asic/INCISIV10.20/tools/uvm-1.1/uvm_lib/uvm_sv \
+UVM_TESTNAME=my_test2 \
$(SRC)

提示三：
用iccr查看和分析覆盖率时，合并多次覆盖率数据的命令需注意：
1. load_test *   直接用“*”就行，如果一定要指定文件名，请指定文件夹的名字test_sv-xxxxxxxxx（cov_work/scope/test_sv-xxxxxxxxx/icc_xxxxxxxx_xxxxxxxx.ucd）
2. merge test_sv-* -output all

提示四：
1. covergroup cg;
    endgroup
    cg = new(); 别忘了用new来初始化covergroup哦。
2. 使用covergroup cg;不带采样控制的语句时（带采样控制是这个样子covergroup cg @(posedge clk); ），
需要在uvm_monitor里使用cg.sample()来采样。
3. 可以使用cg.coverage()来取得实时的覆盖率情况，进而调整约束和控制仿真的结束。

代码如下：

CODE:

class my_subscriber extends uvm_subscriber #(my_transaction);
  `uvm_component_utils(my_subscriber)
  // has implicit analysis_export

  bit reset;
  bit [3:0] cmd;
  bit [7:0] addr;
  bit [7:0] data;

  covergroup cover_bus; //covergroup is like construct
    option.per_instance = 1;
    option.goal = 100;

    cov_reset: coverpoint reset { bins r1[] = {[0:1]}; }

    cov_cmd_0: coverpoint cmd[0] { bins c0[] = {[0:1]}; }
    cov_cmd_1: coverpoint cmd[1] { bins c1[] = {[0:1]}; }
    cov_cmd_2: coverpoint cmd[2] { bins c2[] = {[0:1]}; }
    cov_cmd_3: coverpoint cmd[3] { bins c3[] = {[0:1]}; }

    cov_addr_0: coverpoint addr[0] { bins a1[] = {[0:1]}; }
    cov_addr_1: coverpoint addr[1] { bins a2[] = {[0:1]}; }
    cov_addr_2: coverpoint addr[2] { bins a3[] = {[0:1]}; }
    cov_addr_3: coverpoint addr[3] { bins a4[] = {[0:1]}; }
    cov_addr_4: coverpoint addr[4] { bins a5[] = {[0:1]}; }
    cov_addr_5: coverpoint addr[5] { bins a6[] = {[0:1]}; }
    cov_addr_6: coverpoint addr[6] { bins a7[] = {[0:1]}; }
    cov_addr_7: coverpoint addr[7] { bins a8[] = {[0:1]}; }

    cov_data_0: coverpoint data[0] { bins d0[] = {[0:1]}; }
    cov_data_1: coverpoint data[1] { bins d1[] = {[0:1]}; }
    cov_data_2: coverpoint data[2] { bins d2[] = {[0:1]}; }
    cov_data_3: coverpoint data[3] { bins d3[] = {[0:1]}; }
    cov_data_4: coverpoint data[4] { bins d4[] = {[0:1]}; }
    cov_data_5: coverpoint data[5] { bins d5[] = {[0:1]}; }
    cov_data_6: coverpoint data[6] { bins d6[] = {[0:1]}; }
    cov_data_7: coverpoint data[7] { bins d7[] = {[0:1]}; }
  endgroup: cover_bus

  function new(string name, uvm_component parent);
    super.new(name, parent);
    //new covergroup
    cover_bus = new();
  endfunction: new

  function void write( my_transaction t);
    reset = t.reset;
    cmd = t.cmd;
    addr = t.addr;
    data = t.data;
    //covergroup sample values
    cover_bus.sample();
    $display("my_subscriber| cmd = %h, addr = %h, data= %h, cov=%d\%",
                 cmd, addr, data, cover_bus.get_coverage());
  endfunction: write

endclass: my_subscriber

class my_monitor extends uvm_monitor;
  `uvm_component_utils(my_monitor)

  //declare analysis port
  uvm_analysis_port #(my_transaction) aport;
  virtual dut_if dut_vi;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction: new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    //new aport instance
    aport = new("aport", this);
    //get dut_if
    assert( uvm_config_db #(virtual dut_if)::get(this, "", "dut_vi", dut_vi) );
  endfunction: build_phase

  task run_phase(uvm_phase phase);
    forever
    begin
      my_transaction tx;
      @(posedge dut_vi.clock);
      tx = my_transaction::type_id::create("tx");
      tx.reset = dut_vi.reset;
      tx.cmd = dut_vi.cmd;
      tx.addr = dut_vi.addr;
      tx.data = dut_vi.data;
      //send tx through analysis port
      aport.write(tx);
    end
  endtask: run_phase

endclass: my_monitor