senior verification engineer (成都）

wsguestc · 发表于 2016-1-30 16:35:39

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公司中天联科，具体可在网上查。

公司机顶盒业务部门需要IC 验证人员，内部工作氛围不错。想回成都的可以投简历给我

wsguestc126@126.com

Responsibility:

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Developverification plan according to the Chip/IP specification

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SetupUVM verification environment

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CreateConstrain Random test pattern and direct test pattern to verify DUT

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DevelopUVM Interface VIPs

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Createfunctional coverage by assertion or coverage groups

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Workclosely with RTL designer to assist in simulation debug/code coverage analysis

Qualification:

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Master/Bachelordegree on EE or related with 3+ year experience in verification ,2+ yearexperience on UVM

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Familiarwith Perl/Python, shell programming

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Basicknowledge of IC design, IC production flow

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Experiencein display system or DDR is a plus

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Experiencein chip/SOC level verification is a plus

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Excellentinterpersonal and communication skills, good teamwork adaptability, goodwritten English skills, self-motivated.

wsguestc · 发表于 2016-2-1 15:21:55

待遇和氛围都不错，没有最高工作年限限制

wsguestc · 发表于 2016-2-2 20:57:42

RT RTRT

llj198611 · 发表于 2016-2-2 21:32:08

帮你顶下，哈哈

wsguestc · 发表于 2016-2-3 07:44:50

3楼的是linjun?哈哈

wsguestc · 发表于 2016-2-4 08:52:40

RTRTRT

wsguestc · 发表于 2016-2-17 10:49:49

继续。。。。。。。。。。。

wsguestc · 发表于 2016-2-19 16:02:34

.。。。。。。。。。。。。。。。。。。。。

wsguestc · 发表于 2016-4-22 17:26:44

继续啊。。。。。。。。

zsnradium · 发表于 2016-4-22 20:14:18

HR打了个电话了解了下就没动静了
也不知道是啥意思

[招聘] senior verification engineer (成都）