xilink中PLL的IP核调用出现问题

userofyours

我想要调用ISE的IP核PLL去产生多路不同频率的信号作为不同路径上始终，但是在调用后出现错误，卡在MAP，看了好多帖子没找到解决的办法，有人说是OBUF不能直连，不明白是什么意思，代码就下面的几句话。调用了IP核。最后贴出错误信息。出现了3条这样的信息，大致内容是一致的，求大手子训斥！
module pll_test(


input
wire
sclk,

input
wire
rst_n,

output
wire
out_clk[3:0],

output
wire
locked
    );



wire
oclk;




pll_ip
pll_ip_inst(


.CLK_IN1(sclk),

.RESET(rst_n),

.CLK_OUT1(),

.CLK_OUT2(oclk),

.CLK_OUT3(),

.CLK_OUT4(),

.LOCKED(locked)
);



ERRORlace:1205 - This design contains a global buffer instance,
   <pll_ip_inst/clkout2_buf>, driving the net, <out_clk_0_OBUF>, that is driving
   the following (first 30) non-clock load pins off chip.
   < PIN: out_clk<0>.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "pll_ip_inst/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORlace:1205 - This design contains a global buffer instance,
   <pll_ip_inst/clkout3_buf>, driving the net, <out_clk_1_OBUF>, that is driving
   the following (first 30) non-clock load pins off chip.
   < PIN: out_clk<1>.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "pll_ip_inst/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

userofyours

在线等~~~~~求大手子训斥！

userofyours

没人吗、？好希望有一群一起学习的同伴！

userofyours

还是没人吗？要沉下去了吗

userofyours

我了解了一些，但是还是不知道SPARTAN_6为啥什么会ODDR2影响，我是初学者，一直以为寄存器就可以直接用线wire连接在IO口上，那么在IO口上很容易就能得到PLL输出的不同频率的信号，但是还是太年轻、太天真。
  接下来就这个问题，说几点，在错误当中说，逻辑资源不足，但是写“电路”的我怎么会想到是这几条小小的短短的语句就造成的，我没明白就去看了下官方给的英文的User guide  。里面详细的介绍了ODDR2的使用以及内部的电路，其实在我粗浅的理解还是有点空难，等我看完会，回来继续将这个帖子写出来，也是弥补我的不足，更是让跟多的人明白。

z894811350

我个人认为，pll里面好像都是前两个输出时钟带有bufg，后面的不带有，如果用后面的，需要自己手动添加bufg。
输出信号是reg就应该用reg；同一个信号乱改属性，会出现问题。

yongbyb2000

PIN "pll_ip_inst/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
把这句加到UCF里

feiyuzhuxian

Spartan-6 里面不允许直接输出时钟信号到IO引脚上，要么借助ODDR2，要么使用PIN "pll_ip_inst/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 语句忽略掉

aha007

我也遇到了这个问题，在UCF文件中加入 PIN "clk_gen_inst/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE 后下板测试正确，引脚能用示波器测到时钟信号。但是改用ODDR2后，map通过，下板子测引脚却没有信号输出，求问各位大神这是怎么回事？

anhongliang

你输出的时钟频率是多少？