FPGA& IC-芯得职位20151022

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FPGA高级设计工程师

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

职责描述：

1.  与市场和软件人员合作，参与评估客户需求和制定网络数据包处理板卡的设计方案

2.      负责FPGA的Specification和设计实现

3.      负责板卡的系统验证和联调，协助客户进行测试

职位要求：

1.        有设计用于Ethernet/IP数据包处理的FPGA的工作经验

2.        具有调试由FPGA、CPU 和ASIC组成的板卡的经验和能力。

3.        熟悉PCIe等接口设计

4.        良好的团队合作和敬业精神

5.        有数据网络通信系统设计经验者优先

高级软件工程师

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

职位描述：

1.  SP(Search Processor)的SDK开发，提供SP所实现的各项功能。

2.  理解客户系统中SP的应用和技术要求，设计符合市场需求的API。

3.  为客户提供SP应用相关的技术方案。

职位要求：

1.  能够独立完成SDK和API设计开发工作。

2.  有SDK开发经验，具有开发和优化算法的能力。

3.  熟悉硬件，有linux或者VxWorks底层驱动程序开发经验。

4.  良好的语言沟通能力。

5.  良好的团队合作精神和敬业精神

6.  有路由器、交换机经验，熟悉转发流程和相应的软件，特别是与查找相关的算法和软件经验是big plus。

7.  有TCAM使用方面的工作经验者佳

IC Design Leader/Manager：

[url=mailto:简历发offer@hi-talent.net]简历发offer@hi-talent.net[/url]

Responsibilities:

1.Lead other Design Engineers in a team tomeet the company's objectives；

2. Design and implement digitalcommunication system blocks and whole chip including specification trade-offsand optimization, micro-architecture, RTL coding, Synthesis, STA andsimulation, chip testing and characterization.

3.This is a full-time position with solidequity opportunity.

Requirements:

1.5+ years of experience inVerilog/Synthesis-based ASIC Design for mass production IC chipsExperience withproject and team management

2.Experience from front-end to back-end(RTL, synthesis, verification, and test support) with data networkingASIC(Ethernet, TCP/IP)

3.Verilog language and simulationverification experience

4.Logic Synthesis and Static TimingAnalysis

5.Interface with Place and Route andback-annotated simulation verification

6.Team-work spirit, and with a strong driveto excel

IC Design Engineer：

Responsibilities:

1.Work with other Design Engineers to meetthe company's objectives；

2.Design and implement digitalcommunication system blocks and whole chip including specification trade-offsand optimization, micro-architecture, RTL coding, Synthesis, simulation andverification, chip testing and characterization.

3.This is a full-time position with solidequity opportunity.

Requirements:

1.3+ years of experience inVerilog/Synthesis-based ASIC Design

2.Experience with front to back (RTL,synthesis, verification, and test support) with data networking ASIC(Ethernet,TCP/IP)

3.Verilog language and simulationverification experience

4.Logic Synthesis and Static TimingAnalysis

5.Interface with Place and Route andback-annotated simulation verification

6.Team-work spirit, and with a strong driveto excel

IC Verification Senior Engineer/Lead：

Responsibilities:

1.Compose the verification plan accordingto the chip specification and customer's use cases;

2.Adopt the advanced verification methodologiesto create the whole verification environment from scratch according to therequirements of specific IC;

3.Design Behavioral functional model andtest-benches with C/System C, Verilog/System Verilog and script languages

4.Create, build and implement test caseswith high degree of accuracy to verify Device Under Test

5.Work closely with concept architect andRTL designer to verify RTL design through extensive test-bench simulation formodular and top-level design to obtain very high percentage of functional andcode coverage

6.Work closely with FPGA prototypingapplication and validation engineers to verify functional design

7.Coach the inexperienced engineers in theteam

8.Secondary task may include design ofdigital logic with high-level description language (VHDL/Verilog)  fromspecification.

Requirements:

1.Master's/Bachelor's Degree inElectrical/Electronics or Computer Engineering.

2.5+ years IC verification experience onthe complex ASIC/SOC

3.Experience with advanced verificationmethodologies(VMM, OVM, UVM, etc.) including functional coverage andconstrained random testing

4.Good knowledge of C, SystemC, and atleast one of script languages: Perl, Python, etc.

5.Expert knowledge of VHDL/Verilog HDL andCAD tools (Synopsys and/or Cadence)

6.Team-work spirit, and with a strong driveto excel

7.Able to work independently on a givenassignment and work hard to finish on time

8.Good written and communication skills

9.Previous experience on data networkcommunication IC is an added advantage

IC Verification Engineer

[url=mailto:简历发offer@hi-talent.net]简历发offer@hi-talent.net[/url]：

Responsibilities:

1.Compose the pre-silicon verification planaccording to the chip specification and customer's use cases

2.Design Behavioral functional model andtest-benches with C/System C. HDL and script languages

3.Create. build and implement test caseswith high degree of accuracy to verify Device Under Test

4.Work closely with concept architect and RTLdesigner to verify RTL design through extensive testbench simulation formodular and top-level design to obtain very high percentage of functional andcode coverage

5.Work closely with FPGA prototypingapplication and validation engineers to verify functional design

6.Coach the inexperienced interns in theteam

7.Secondary task may include design ofdigital logic with high-level description language (VHDL/Verilog) fromspecification.

Requirements:

1,Master's/Bachelor's Degree inElectrical/Electronics or Computer Engineering.

2,Experience with verificationmethodologies including functional coverage and constrained random testing

3,Good knowledge of C, SystemC, and atleast one of script languages: Perl, Python, etc.

4,Expert knowledge of VHDL/Verilog HDL andCAD tools (Synopsys and/or Cadence)

5,Team-work spirit, and with a strong driveto excel

6,Able to work independently on a givenassignment and work hard to finish on time

7,Good written and communication skills

8,Previous experience in data communicationnetwork IC area is an added advantage

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

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