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【猎头职位:成都需要一位 Verification Team Leader】联系人:Judy-Wu,邮箱:hr@kthr.com,微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注! Responsibility: Write the verification plan according to the Chip/IP specification; Setup the whole verification environment with the advanced verification methodologies; Design the behavioral functional model with Verilog/System Verilog, C/System C; Create the direct test pattern and constrained random test pattern to test the DUT; Work closely with RTL designer to assist in simulation debug/code coverage analysis.
Qualification: Master/Bachelor degree on Electrical/Electronics, Computer Engineering or C-ommunication; Minimum of five years experiences on IC Design/verification/emulation experiences; Experience on VMM/OVM/UVM and knowledge of VIP are preferred; Familiar with Perl/Python, shell programming and excel operation is a plus .Expert knowledge of C/C++/SystemC ,VHDL/Verilog HDL, HVL(systemverilog) and simulation tools; Able to setup the verification environment and verification flow independently; Basic knowledge of logic and circuit design, knowledge of microprocessors and computer system architecture is a plus; Proactively learner and eager for new technologies; Excellent interpersonal and communication skills, good teamwork adaptability, good written English skills, self-motivated.
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