ABSTRACT:
CMOS VLSI circuit reliability modeling and simulation have attracted intense
research interest in the last two decades, and as a result almost all IC Design For
Reliability (DFR) tools now try to incrementally simulate device wearout mecha-
nisms in iterative ways. These DFR tools are capable of accurately characterizing
the device wearout process and predicting its impact on circuit performance. Never-
theless, excessive simulation time and tedious parameter testing process often limit
popularity of these tools in product design and fabrication.
This work develops a new SPICE reliability simulation method that shifts the
focus of reliability analysis from device wearout to circuit functionality. A set of
accelerated lifetime models and failure equivalent circuit models are proposed for
the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier
Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias
Temperature Instability (NBTI). The accelerated lifetime models help to identify
the most degraded transistors in a circuit in terms of the device's terminal voltage
and current waveforms. Then corresponding failure equivalent circuit models are in-
corporated into the circuit to substitute these identi¯ed transistors. Finally, SPICE
simulation is performed again to check circuit functionality and analyze the impact
of device wearout on circuit operation. Device wearout e®ects are lumped into a
very limited number of failure equivalent circuit model parameters, and circuit per-
formance degradation and functionality are determined by the magnitude of these
parameters.
In this new method, it is unnecessary to perform a large number of small-step
SPICE simulation iterations. Therefore, simulation time is obviously shortened in
comparison to other tools. In addition, a reduced set of failure equivalent circuit
model parameters, rather than a large number of device SPICE model parameters,
need to be accurately characterized at each interim wearout process. Thus device
testing and parameter extraction work are also signi¯cantly simpli¯ed. These ad-
vantages will allow circuit designers to perform quick and e±cient circuit reliability
analyses and to develop practical guidelines for reliable electronic designs. |