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本帖最后由 sailorchu 于 2015-8-28 09:03 编辑
要求:通信计算机等相关专业,本科及以上学历。
应届毕业生也可以,但最好是硕士及以上。
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一 算法:通信相关的,wifi经验优先。
Responsibilities:
1. Wifi 基带算法的性能仿真和性能评估
2. 基带算法的优化
3. 协助基带算法的实现和数据比对
4. 协助芯片的测试:RF或基带
Requirements:
1.熟悉无线通信处理的过程
2.熟悉无线基带算法
3.熟练掌握Matlab或C,C++
4.有verilog hdl编程经验的优先考虑
5.有SoC经验的优先考虑
6.有Wifi芯片开发经验的优先考虑
二 asic Engineer:数字逻辑工程师,懂嵌入式系统或者通信算法者优先。
Responsibilities:
Primary (70%):
1. Provide detailed block-level design and documents;
2. Develop and execute thorough block level simulation and lab verification plan;
3. Participate in the FPGA platform development and lab debugging.
Secondary (30%):
1. Participate in block level architecture design;
2. Assisting embedded FW development.
Requirements:
Experience/Skills:
1. Strong analytical, and problem solving skills as well as hands-on lab debugging skills.
2. Good knowledge of RTL design and simulation.
3. Able to write C code to model RTL blocks for simulation and verification.
4. Able to write reusable Verilog RTL codes, follow design and DFT guidelines.
5. Able to run synthesis, static timing analysis and formal verification is highly desirable, but not required.
6. Knowledge in languages relevant to the ASIC development process including Verilog, Unix Scripting, Perl and Tcl is strong plus.
7. dsp function implementation experience is a plus, but not required.
8. Good communication skills, especially in technical writing and reporting
9. Self-motivated and ability to excel in a team environment.
有意向的请把简历发到我邮箱:sailor.chu@ovt.com
OV欢迎您的加入!! |
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