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ASIC Engineer of SOC and Video system
简历
发
芯得 boss@hi-talent.com
Requirements
1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chipexperience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related ispreferred
a) IP level micro-architecture definition, RTL design, co-work withverification owner
5. Nice to have experience of chip level clock/reset structure definition, lowpower partition definition
6. Good team work and communication skill (both in Chinese and English).
Responsibility
The candidate will be working on one of following items
1. SOC architecture definition and coordination including clock/reset structuredefinition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTLdesign, co-work with verification owner
Best Regards Jane.Jin 金娟 Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd. 上海芯得企业管理咨询有限公司 上海芯相会企业管理咨询有限公司 Mob: 18502155252 E-Mail: Jane-Jin@hi-talent.com 微信: xinde_jane QQ: 1600548210 Weibo: http://weibo.com/u/1716864892 webside:
www.hi-talent.cn
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