逐点半导体（上海）有限公司 高新诚聘

wangjl

Pixelworks（美国像素科技有限公司）1997年成立于美国俄勒冈州，是数字显示行业内著名的系统级芯片提供商。于2000年在高科技股云集的美国NASDAQ上市，在上市当年即成为半导体行业在NASDAQ上市融资最多的公司。Pixelworks的产品广泛应用于包括液晶显示器、液晶电视、多媒体投影仪、PDP电视、背投影电视、高清晰度电视等商用和民用的CRT显示和数字平板显示设备中。公司总部位于俄勒冈州图拉丁市，在硅谷、东京、汉城、台北、伦敦、深圳，北京和上海设有代表处。主要客户包括康柏、戴尔、三星、索尼、东芝、爱普生、飞利浦等国际著名品牌。 Pixelworks在国际视频图形图像处理技术领域以技术精湛著名，在该领域内拥有多项技术专利，包括精密缩放，隔行逐行格式变换，数字降噪，视频图像增强等，此外Pixelworks还拥有与技术齐肩的市场反应速度、客户服务质量、开放的工作气氛和鼓励创新、激励进取和团队精神的工作氛围。

工作地点：上海     邮箱：mina@jobic.cn

Sr./Staff verification Engineer

Qualifications:

5+ years of ASIC verification experience, complex SOC verification experience is preferred

Strong programming skills in SystemVerilog

Knowledgeable in Verilog/Verilog-PLI/SystemC/SVA/C/C++

Working Experience with UVM/OVM/VMM (at least one of them)

Responsible for implementation of verification environment and generation of high quality test cases.

BS/MS EE, CE or CS

Sr. DSP Engineer

Implement and optimize video and image processing algorithm based on OpenGL, OpenCL, or based on CPU and CPU’s coprocessor on android os or iOS.

Requirement:

Familiar with OpenGL, OpenCL
Familiar Game Engine
Familiar with Graphics and Display related technology of android OS or iOS.
岗位要求
Requirement:

Familiar with OpenGL, OpenCL
Familiar Game Engine
Familiar with Graphics and Display related technology of android OS or iOS.

Sr. IC Engineer

职位描述
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner
岗位要求
Requirements

1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).

wangyukan

顶，UVM实践的作者 张强在的公司？

rumi

顶！图像处理梆梆的。

chineselboy

好像 已经被天朝拿下了吧？

chen1q

请问需要版图工程师吗？