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本帖最后由 ariabell 于 2015-7-16 09:24 编辑
Job Title：Synopsys DDR PHY verification Manager (Digital)
Location：Wuhan
Email:jobs-china@synopsys.com
Job description This position will be leading a local verification team to develop verification platform for Synopsys leading edge interface IP. Verification development tasks include verification plan development, test bench generation in VMM/UVM/SystemVerilog/C++, test cases development and debug, test environment infra and regression infra development.
The position will have to coordinate with various engineering teams across Synopsys to drive IP development and successful release with high quality; Combine PHY IP development verification process and improve team’s verification technical capabilities; Expand team’s bandwidth by recruiting excellent engineers; and execute on ASIC/SOC verification flow to meet project release quality and schedule requirement.
Requirements MSEE required and 8+ years of verification working experience. Hands on experience with creating test plan and test environment from Functional Specifications/ Test Environment Specifications with verification methodology of VMM/UVM.
Has leadership skills and takes ownership on projects.
Has Good analysis and problem-solving skills.
Has ability to improve work flow and quality.
Has both of good verbal and written communication skills to work with global teams.
Interface IP development experience is a big plus.
Management experience is a big plus.
欢迎将简历投递到 jobs-china@synopsys.com. | 
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发表于 2015-7-15 17:34:16
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