ESD Protection Design With Low-Capacitance for high Frequency (by Ming-Dou Ker)

semico_ljj

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-
Frequency I/O Interfaces in Integrated Circuits

Ming-Dou Ker

Abstract: Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics,
especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been
one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD
protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore,
ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to
sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are
addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and
discussed.

Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator,LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme, substrate-triggering technique, silicon-controlled rectifier (SCR), waffle structure.

Received: December 13, 2006; Accepted: April 4, 2007; Revised: April 4, 2007

lishang

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semico_ljj

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不叫的猫

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