Error：it does not hold its value outside the clock edge

smattershi

Rd_FIFO_Clk_Num_Proc:
  process (Reset,Clk16X)
  begin
   if (Reset='1') then
       DOUT_FIFO <= (others => '1');   
       After_RD_CLK <= (others => '0');
   -- elsif rising_edge(Clk16X) then
elsif (ADDR_s = A_RBR) and (RDn_cs = '0')then
   if rising_edge(Clk16X) then
     After_RD_CLK <=  After_RD_CLK + 1;
   end if;   
   DOUT_FIFO <= RXFIFOQ;
    else
        DOUT_FIFO <= (others => '1');   
        After_RD_CLK <= (others => '0');
    end if;
  end process Rd_FIFO_Clk_Num_Proc;   

把红色部分换成

elsif rising_edge(Clk16X) then
if (ADDR_s = A_RBR) and (RDn_cs = '0')then
在综合的时候 就会报错

Error (10001): Verilog HDL or VHDL error at intface.vhd(574): can't infer register for After_RD_CLK[0] because it does not hold its value outside the clock edge
点击报错信息是在紫色的 reset 语句
谁能告诉我怎么会这样呢？