招聘IC layout engineer

teradyne

IC layout engineer
IC layout engineer

成都芯源系统有限公司
  
IC layout engineer  


发布日期： 2007-04-16 工作地点： 成都市

招聘人数： 2

外语要求： 英语  薪水范围： 面议

学    历： 本科 接受简历语言： 中文和英文


职位描述：
Job Description:
IC Layout Engineer

Responsibilities include layout of analog/mixed signal IC,

DRC/LVS verification, block/chip floor plan, power/clock distribution and chip assembly.

Requirements:
1. BSEE preferred.
2. Cadence layout design tools.
3. DRC/LVS tools.
4. Bipolar and CMOS process.
5. Good communication skill in English and Chinese.
6. Both Chinese and English resumes are acceptale.


rg如果有人感兴趣，请联系我，我可以推荐你：teradyne@gmail.com

[ 本帖最后由 teradyne 于 2007-4-18 11:47 编辑 ]