verilog语法问题

chang75161

module aaaaaa  #(parameter size=2)（output reg a_gt_b,a_lt_b,a_eq_b,input[size-1:0]a,b);
integer k;
always@(a,b)begin:compare_loop
for(k=size;k>0;k=k-1)begin
if(a[k]!=b[k])begin
a_gt_b=a[k];
a_lt_b=~a[k];
a_eq_b=0;
disable compare_loop;
end
end
a_gt_b=0;
a_lt_b=0;
a_eq_b=1;
end
endmodule

ERROR:HDLCompiler:806 - "H:/isefunction/aaaaaa/aaaaaa.v" Line 21: Syntax error near "�"ERRORrojectMgmt - 1 error(s) found while parsing design hierarchy.  就是第一行，怎么错啦，求解答

richardxingxing

你得有个模块调用这个参数化设计的模块

xduryan

一行一个信号，好好写